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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 19-5657; rev 1; 1/11 typical applications circuit appears at end of data sheet. general description the max9270 deserializer uses maxims gigabit multimedia serial link (gmsl) technology. the device functions the same as the max9260 deserializer without an output enable ( enable ) pin. outputs are enabled or disabled by a register bit. the deserializer pairs with any gmsl serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data. the deserializer accepts a maximum serial payload data rate of 2.5gbps for a 15m shielded twisted-pair (stp) cable. the 24-bit or 32-bit width parallel interface operates up to a maximum bus clock of 104mhz or 78mhz, respectively. this serial link supports display panels from qvga (320 x 240) up to xga (1280 x 768), or dual-view wvga (2 x 854 x 480). the 24-bit or 32-bit mode handles 21 or 29 bits of data, along with an i 2 s input, supporting 4- to 32-bit audio word lengths and an 8khz to 192khz sample rate. the embedded control channel forms a full-duplex, differen - tial 100kbps to 1mbps uart link between the serializer and deserializer. the host electronic control unit (ecu) or microcontroller ( f c) resides either on the serializer (for video display) or the deserializer (for image sensing). in addition, the control channel enables ecu/ f c control of peripherals in the remote side of the serial link through i 2 c (base mode) or a user-defined full-duplex uart format (bypass mode). the channel equalizer extends the link length and enhances the link reliability. spread spectrum is avail - able to reduce emi on the parallel output data signals. the differential link complies with the iso 10605 and iec 61000-4-2 esd-protection standards. this device uses a 3.3v core supply and a 1.8v to 3.3v i/o supply. the device is available in a 56-pin tqfn package (8mm x 8mm x 0.75mm) with an exposed pad. electrical performance is guaranteed over the -40 n c to +105 n c automotive temperature range. applications high-speed serial-data transmission for display high-speed serial-data transmission for image sensing automotive navigation, infotainment, and image- sensing systems features s pairs with any gmsl serializer s 2.5gbps payload rate, ac-coupled serial link with 8b/10b line coding s 24-bit or 32-bit programmable parallel output bus supports up to xga (1280 x 768) or dual-view wvga (2 x 854 x 480) panels with 18-bit or 24-bit color s 8.33mhz to 104mhz (24-bit bus) or 6.25mhz to 78mhz (32-bit bus) parallel data rate s support two/three 10-bit camera links at 104mhz/78mhz maximum pixel clock s 4-bit to 32-bit word length, 8khz to 192khz i 2 s audio channel supports high-definition audio s embedded half-/full-duplex bidirectional control channel (100kbps to 1mbps) s separate interrupt signal supports touch-screen functions for display panels s remote-end i 2 c master for peripherals s line equalizer extends link length s programmable spread spectrum on the parallel data outputs reduce emi s does not require an external clock s auto data-rate detection allows on-the-fly data-rate change s built-in prbs checker for ber testing s iso 10605 and iec 61000-4-2 esd protection s -40 n c to +105 n c operating temperature range s patent pending ordering information /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. part temp range pin-package max9270gtn/v+ -40 n c to +105 n c 56 tqfn-ep*
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to ep .......................................................... -0.5v to +3.9v dvdd to ep .......................................................... -0.5v to +3.9v iovdd to ep ......................................................... -0.5v to +3.9v in+, in- to ep ....................................................... -0.5v to +1.9v all other pins to ep .............................. -0.5v to (iovdd + 0.5v) in+, in- short circuit to ground or supply .................................................................... continuous continuous power dissipation (t a = +70 n c) 56-pin tqfn (derate 47.6mw/ n c above +70 n c) .... 3809.5mw esd protection human body model (r d = 1.5k i , c s = 100pf) (in+, in-) to ep ............................................................. q 8kv all other pins to ep ...................................................... q 4kv iec 61000-4-2 (r d = 330 i , c s = 150pf) contact discharge (in+, in-) to ep ............................................................. q 8kv air discharge (in+, in-) to ep ........................................................... q 10kv iso 10605 (r d = 2k i , c s = 330pf) contact discharge (in+, in-) to ep ............................................................ q 8kv air discharge (in+, in-) to ep ........................................................... q 20kv operating temperature range ........................ -40 n c to +105 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings 56 tqfn junction-to-ambient thermal resistance ( ja ) .......... 21 n c/w junction-to-case thermal resistance ( jc ) ................. 1 n c/w dc electrical characteristics (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) package thermal characteristics (note 1) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units single-ended inputs ( enable , int, pwdn , ssen, bws, es, drs, ms, cds, eqs, dcs) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0 to v iovdd -10 +10 f a input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (dout_, sd, ws, sck, pclkout) high-level output voltage v oh i oh = -2ma v dcs = v gnd v iovdd - 0.3 v v dcs = v iovdd v iovdd - 0.2 low-level output voltage v ol1 i ol = 2ma v dcs = v gnd 0.3 v v dcs = v iovdd 0.2
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units output short-circuit current i os dout_, sd, ws, sck v o = 0v, v dcs = v gnd v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 13 v o = 0v, v dcs = v iovdd v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 pclkout v o = 0v, v dcs = v gnd v iovdd = 3.0v to 3.6v 15 33 50 v iovdd = 1.7v to 1.9v 5 10 17 v o = 0v, v dcs = v iovdd v iovdd = 3.0v to 3.6v 30 54 97 v iovdd = 1.7v to 1.9v 9 16 32 i 2 c and uart i/o, open-drain outputs (rx/sda, tx/scl, err , gpio_, lock) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0 to v iovdd (note 2) rx/sda, tx/scl -110 +1 f a gpio, err , lock -80 +1 low-level open-drain output voltage v ol2 i ol = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 v differential outputs for reverse control channel (in+, in-) differential high output peak voltage, (v in +) - (v in -) v roh no high-speed data transmission (figure 1) 30 60 mv differential low output peak voltage, (v in +) - (v in -) v rol no high-speed data transmission (figure 1) -60 -30 mv differential inputs (in+, in-) differential high input threshold (peak), (v in +) - (v in -) v idh(p) (figure 2) 40 90 mv differential low input threshold (peak), (v in +) - (v in -) v idl(p) (figure 2) -90 -40 mv input common-mode voltage, ((v in +) + (v in -))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r i 80 100 130 i
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 4 ______________________________________________________________________________________ ac electrical characteristics (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) dc electrical characteristics (continued) (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units parallel clock output (pclkout) clock frequency f pclkout v bws = v gnd , v drs = v iovdd 8.33 16.66 mhz v bws = v gnd , v drs = v gnd 16.66 104 v bws = v iovdd , v drs = v iovdd 6.25 12.5 v bws = v iovdd , v drs = v gnd 12.5 78 clock duty cycle dc t high /t t or t low /t t (figure 4) 40 50 60 % clock jitter t j period jitter, rms, spread off, 3.125gbps, prbs pattern, ui = 1/f pclkout 0.05 ui i 2 c/uart port timing output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns input setup time t set i 2 c only (figure 5) 100 ns input hold time t hold i 2 c only (figure 5) 0 ns parameter symbol conditions min typ max units power supply worst-case supply current (figure 3) i wcs v bws = v gnd , f pclkout = 16.6mhz 2% spread spectrum active 113 166 ma spread spectrum disabled 105 155 v bws = v gnd , f pclkout = 33.3mhz 2% spread spectrum active 122 181 spread spectrum disabled 110 165 v bws = v gnd , f pclkout = 66.6mhz 2% spread spectrum active 137 211 spread spectrum disabled 120 188 v bws = v gnd , f pclkout = 104mhz 2% spread spectrum active 159 247 spread spectrum disabled 135 214 sleep-mode supply current i ccs 80 130 f a power-down supply current i ccz v pwdn = v gnd 19 70 f a
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 _______________________________________________________________________________________ 5 ac electrical characteristics (continued) (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units switching characteristics pclkout rise-and-fall time t r , t f 20% to 80%, v iovdd = 1.7v to 1.9v v dcs = v iovdd , c l = 10pf 0.4 2.2 ns v dcs = v gnd , c l = 5pf 0.5 2.8 20% to 80%, v iovdd = 3.0v to 3.6v v dcs = v iovdd , c l = 10pf 0.25 1.7 v dcs = v gnd , c l = 5pf 0.3 2.0 parallel data rise-and-fall time (figure 6) t r , t f 20% to 80%, v iovdd = 1.7v to 1.9v v dcs = v iovdd , c l = 10pf 0.5 3.1 ns v dcs = v gnd , c l = 5pf 0.6 3.8 20% to 80%, v iovdd = 3.0v to 3.6v v dcs = v iovdd , c l = 10pf 0.3 2.2 v dcs = v gnd , c l = 5pf 0.4 2.4 deserializer delay t sd spread spectrum enabled (figure 7) 2880 bits spread spectrum disabled (figure 7) 750 lock time t lock spread spectrum enabled (figure 8) 1500 f s spread spectrum off (figure 8) 1000 power-up time t pu (figure 9) 2500 f s reverse control-channel output rise time t r no high-speed transmission (figure 1) 180 400 ns reverse control-channel output fall time t f no high-speed transmission (figure 1) 180 400 ns i 2 s output timing ws jitter t aj-ws t ws = 1/f ws , rising (falling) edge to falling (rising) edge (note 3) f ws = 48khz or 44.1khz 0.4e - 3 x t ws 0.5e - 3 x t ws ns f ws = 96khz 0.8e - 3 x t ws 1e - 3 x t ws f ws = 192khz 1.6e - 3 x t ws 2e - 3 x t ws sck jitter t aj-sck t sck = 1/f sck , ris - ing edge to rising edge n ws = 16 bits, f ws = 48khz or 44.1khz 13e - 3 x t sck 16e - 3 x t sck ns n ws = 24 bits, f ws = 96khz 39e - 3 x t sck 48e - 3 x t sck n ws = 32 bits, f ws = 192khz 0.1 x t sck 0.13 x t sck
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 6 ______________________________________________________________________________________ typical operating characteristics (v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c, unless otherwise noted.) note 2: minimum i in due to voltage drop across the internal pullup resistor. note 3: rising to rising edge jitter can be twice as large. ac electrical characteristics (continued) (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) maximum pclkin frequency vs. stp cable length (ber < 10 -9 ) cable length (m) frequency (mhz) 15 10 5 20 40 60 80 100 120 0 0 20 max9270 toc06 optimum pe/eq settings ber can be < 10 -12 for cable lengths less than 10m no pe, eqs = low no pe, eqs = high output power spectrum vs. pclkout frequency pclkout frequency (mhz) pclkout output power (dbm) 44 43 40 41 42 -70 -60 -50 -40 -30 -20 -10 0 -80 39 45 max9270 toc05 0% spread 4% spread 2% spread f pclkout = 42mhz supply current vs. pclkout frequency (32-bit mode) pclkout frequency (mhz) supply current (ma) 65 50 20 35 110 120 130 140 160 150 170 180 100 5 80 max9270 toc04 2%, 4% spread no spread supply current vs. pclkout frequency (24-bit mode) pclkout frequency (mhz) supply current (ma) 85 65 45 25 110 115 120 125 130 135 140 145 150 155 105 5 105 max9270 toc01 all equalizer settings supply current vs. pclkout frequency (24-bit mode) pclkout frequency (mhz) supply current (ma) 85 65 25 45 110 120 130 140 160 150 170 180 100 5 105 max9270 toc03 2%, 4% spread no spread supply current vs. pclkout frequency (32-bit mode) pclkout frequency (mhz) supply current (ma) 65 50 35 20 110 115 120 125 130 135 140 145 150 155 105 5 80 max9270 toc02 all equalizer settings parameter symbol conditions min typ max units audio skew relative to video ask video and audio synchronized 3 x t ws 4 x t ws s sck, sd, ws rise-and-fall time t r , t f 20% to 80% v dcs = v iovdd , c l = 10pf 0.3 3.1 ns v dcs = v gnd , c l = 5pf 0.4 3.8 ns sd, ws valid time before sck t dvb t sck = 1/f sck (figure 11) 0.35 x t sck 0.5 x t sck ns sd, ws valid time after sck t dva t sck = 1/f sck (figure 11) 0.35 x t sck 0.5 x t sck ns
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 _______________________________________________________________________________________ 7 pin configuration pin description top view max9270 tqfn 15 17 16 18 19 20 21 22 23 24 25 26 27 28 tx/scl pwdn err lock ws sck sd dout28/mclk dout27 dout26 dout25 iovdd dout24 dout23 avdd drs ssen dout0 dout1 dout2 dout3 dout4 dout5 dout6 dout7 iovdd dout8 dout9 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ms dvdd rx/sda dcs gpio1 eqs in- in+ avdd es gpio0 cds int bws dout20 dout21 dout22 dout19 dout18 dout17 dout16 pclkout dout15 dout14 dout13 dout12 dout11 dout10 + ep* *connect ep to ground plane pin name function 1 bws bus-width select. parallel output bus-width selection input requires external pulldown or pullup resistors. set bws = low for 24-bit bus mode. set bws = high for 32-bit bus mode. 2 int interrupt. interrupt input requires external pulldown or pullup resistors. a transition on the int input of the deserializer toggles the serializers int output. 3 cds control-direction selection. control-link-direction selection input requires external pull - down or pullup resistors. set cds = low for f c use on the serializer side of the serial link. set cds = high for f c use on the deserializer side of the serial link. 4 gpio0 gpio0. open-drain general-purpose input/output with internal 60k i pullup resistors to iovdd. gpio0 is high impedance during power-up and when pwdn = low. 5 es edge select. pclkout edge-selection input requires external pulldown or pullup resistors. set es = low for a rising-edge trigger. set es = high for a falling-edge trigger.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 8 ______________________________________________________________________________________ pin description (continued) pin name function 6, 56 avdd 3.3v analog power supply. bypass avdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smallest value capacitor closest to avdd. 7, 8 in+, in- differential cml input +/- . differential inputs of the serial link. 9 eqs equalizer select. deserializer equalizer-selection input requires external pulldown or pullup resistors. the state of eqs latches upon power-up or rising edge of pwdn . set eqs = low for 10.7db equalizer boost (eqtune = 1001). set eqs = high for 5.2db equalizer boost (eqtune = 0100). 10 gpio1 gpio1. open-drain general-purpose input/output with internal 60k i pullup resistors to iovdd. gpio1 is high impedance during power-up and when pwdn = low. 11 dcs drive current select. driver current-selection input requires external pulldown or pullup resistors. set dcs = high for stronger parallel data and clock output driv - ers. set dcs = low for normal parallel data and clock drivers (see the dc electrical characteristics table). 12 ms mode select. control-link mode-selection/autostart mode selection input requires external pulldown or pullup resistors. ms sets the control-link mode when cds = high (see the control-channel and register programming section). set ms = low to select base mode. set ms = high to select the bypass mode. ms sets autostart mode when cds = low (see tables 13 and 14). 13 dvdd 3.3v digital power supply. bypass dvdd to ep with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. 14 rx/sda receive/serial data. uart receive or i 2 c serial-data input/output with internal 30k i pullup to iovdd. in uart mode, rx/sda is the rx input of the deserializers uart. in i 2 c mode, rx/sda is the sda input/output of the serializers i 2 c master. 15 tx/scl transmit/serial clock. uart transmit or i 2 c serial-clock output with internal 30k i pullup to iovdd. in uart mode, tx/scl is the tx output of the serializers uart. in i 2 c mode, tx/scl is the scl output of the deserializers i 2 c master. 16 pwdn power-down. active-low power-down input requires external pulldown or pullup resis - tors. 17 err error. active-low open-drain video data error output with internal pullup to iovdd. err goes low when the number of decoding errors during normal operation exceed a programmed error threshold or when at least one prbs error is detected during prbs test. err is high impendence when pwdn = low. 18 lock open-drain lock output with internal pullup to iovdd. lock = high indicates plls are locked with correct serial-word-boundary alignment. lock = low indicates plls are not locked or incorrect serial-word-boundary alignment. lock remains low when the configuration link is active. lock is high impedance when pwdn = low. 19 ws word select. i 2 s word-select output. 20 sck serial clock. i 2 s serial-clock output 21 sd serial data. i 2 s serial-data output. disable i 2 s to use sd as an additional data output latched on the selected edge of pclkout.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 _______________________________________________________________________________________ 9 pin description (continued) pin name function 22C25, 27C35, 37C44, 46C53 dout28/mclk, dout27, dout26, dout25, dout24Cdout16, dout15Cdout8, dout7Cdout0 data output[0:28]. parallel data outputs. output data can be strobed on the selected edge of pclkout. set bws = low (24-bit mode) to use dout0Cdout20 (rgb and sync). dout21Cdout28 are not used in 24-bit mode and are set to low. set bws = high (32-bit mode) to use dout0Cdout28 (rgb, sync, and two extra outputs). dout28 can be used to output mclk (see the additional mclk output for audio applications section). 26, 45 iovdd 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to iovdd. 36 pclkout parallel clock output. used for dout0Cdout28. 54 ssen spread-spectrum enable. parallel output spread-spectrum enable input requires external pulldown or pullup resistors. the state of ssen latches upon power-up or when resuming from power-down mode ( pwdn = low). set ssen = high for q 2% spread spectrum on the parallel outputs. set ssen = low to use the parallel outputs without spread spectrum. 55 drs data-rate select. data-rate range-selection input requires external pulldown or pullup resistors. set drs = high for parallel input data rates of 8.33mhz to 16.66mhz (24-bit mode) or 6.25mhz to 12.5mhz (32-bit mode). set drs = low for parallel input data rates of 16.66mhz to 104mhz (24-bit mode) or 12.5mhz to 78mhz (32-bit mode). ep exposed pad. ep functions as the ics ground connection. must connect ep to the ground plane to maximize thermal and electrical performance.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 10 _____________________________________________________________________________________ functional diagram filter pll audio fifo prbs gen spread pll line- fault det cml tx p s 8b/10b encode parity fifo din[n:0] ws, sd, sck out+ out- lmn0 lmn1 pclkin tx/scl rx/sda clkdiv uart/i 2 c term rev ch rx lflt spread pll audio fifo prbs check cdr pll eq cml rx p s 8b/10b decode parity fifo dout[n:0] ws, sd, sck in- stp cable (z 0 = 50) in+ pclkout gmsl serializer deserializer tx/scl rx/sda clkdiv uart/i 2 c term rev ch tx max9270
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 11 figure 1. reverse control-channel output parameters figure 2. test circuit for differential input measurement figure 3. worst-case pattern output max9270 reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + pclkout dout_ note: pclkout programmed for rising latch edge.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 12 _____________________________________________________________________________________ figure 4. clock output high-and-low times figure 6. output rise-and-fall times figure 5. i 2 c timing parameters v ol max t high t low t t v oh min pclkout 0.8 x v i0vdd 0.2 x v i0vdd t f t r c l single-ended output load max9270 p t r p s s t hold t f t set tx/ scl rx/ sda
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 13 figure 7. deserializer delay figure 8. lock time figure 9. power-up delay first bit in+/- dout_ pclkout last bit serial word n serial-word length serial word n+1 serial word n+2 t sd parallel word n-2 parallel word n-1 parallel word n note: pclkout programmed for rising latching edge. in+ - in- lock t lock pwdn must be high v oh in+/- lock t pu pwdn v oh v ih1
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 14 _____________________________________________________________________________________ figure 10. output i 2 s timing parameters detailed description the max9270 deserializer utilizes maxims gmsl tech - nology. this device pairs with any gmsl serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data for video- display or image-sensing applications. the max9270 functions the same as the max9260 without an output enable pin ( enable ). outputs are enabled by default and programmable by a register bit. the serial-payload data rate can reach up to 2.5gbps for a 15m stp cable. the parallel interface is programmable for 24-bit or 32-bit width modes at the maximum bus clock of 104mhz or 78mhz, respectively. the minimum bus clock is 6.25mhz for the 32-bit mode and 8.33mhz for the 24-bit mode. with such a flexible data configuration, the gmsl is able to support xga (1280 x 768) or dual-view wvga (2 x 854 x 480) display panels. for image sensing, it supports three 10-bit camera links simultaneously with a pixel clock up to 78mhz. the 24-bit mode handles 21-bit data and control signals plus an i 2 s audio signal. the 32-bit mode handles 29-bit data and control signals plus an i 2 s audio signal. any combination and sequence of color video data, video sync, and control signals make up the 21-bit or 29-bit parallel data on dout_. the i 2 s port supports the sampled audio data at a rate from 8khz to 192khz and the audio word length of anywhere between 4 to 32 bits. the embedded control channel forms a uart link between the serializer and deserializer. the uart link can be set to half-duplex mode or full-duplex mode depending on the application. the gmsl supports uart rates from 100kbps to 1mbps. using this control link, a host ecu or f c communicates with the serializer and deserializer, as well as the peripherals in the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. all serial communication (forward and reverse) uses differential signaling. the peripheral programming uses i 2 c format or the default gmsl uart format. a separate bypass mode enables communication using a full-duplex, user- defined uart format. the control link between the serializer/deserializer allows f c connectivity to either device or peripherals to support video-display or image- sensing applications. the ac-coupled serial link uses 8b/10b coding. the deserializer features a programmable channel equalizer to extend the link length and enhance the link reliability. a programmable spread-spectrum feature reduces emi on the parallel data outputs. the differential serial link input pins comply with the iso 10605 and iec 61000-4-2 esd-protection standards. this device uses a 3.3v core supply and a 1.8v to 3.3v i/o supply. register mapping the f c configures various operating conditions of the gmsl through registers in the serializer/deserializer. the default device addresses stored in the r0 and r1 registers of the serializer/deserializer are 0x80. write to the r0/r1 registers to change the device address of the serializer or deserializer. ws t dva t dvb t dva t f t dvb t r sck sd
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 15 table 1. power-up default register map (see table 12) register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x80 serid =1000000, serializer device identifier is 1000 000 reserved = 0 0x01 0x90 desid =1001000, deserializer device identifier is 1001 000 reserved = 0 0x02 0x1f or 0x5f ss = 00 (ssen = low), ss = 01 (ssen = high), spread-spectrum settings depend on ssen pin state at power-up reserved = 0 audioen = 1, i 2 s channel enabled prng = 11, automatically detect the pixel clock range srng = 11, automatically detect serial-data rate 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after locking reserved = 0 sdiv = 00000, autocalibrate sawtooth divider 0x04 0x03 or 0x83 locked = 0, lock output = low (read only) outenb = 0, outputs enabled prbsen = 0, prbs test disabled sleep = 0 or 1, sleep setting default depends on cds and ms pin state at pow - er-up (see the link startup procedure section) inttype = 00, base mode uses i 2 c revccen = 1, reverse control channel active (sending) fwdccen = 1, forward control channel active (receiving) 0x05 0x28 or 0x29 reserved = 0 hpftune = 01, 3.75mhz equalizer highpass cutoff frequency pdhf = 0, high-frequency boosting disabled eqtune = 1000 (eqs = high, 10.7db), eqtune = 1001 (eqs = low, 5.2db), eqtune default setting depends on eqs pin state at power-up 0x06 0x0f disstag = 0, staggered outputs enabled autorst = 0, error registers/output auto reset disabled disint = 0, int transmission enabled int = 0, int output = low (read only) gpio1out = 1, gpio1 output set to high gpio1 = 1, gpio1 input = high (read only) gpio0out = 1, gpio0 output set to high gpio0 = 1, gpio0 input = high (read only) 0x07 0x54 reserved = 01010100 0x08 0x30 reserved = 00110000 0x09 0xc8 reserved = 11001000 0x0a 0x12 reserved = 00010010 0x0b 0x20 reserved = 00100000
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 16 _____________________________________________________________________________________ table 1. power-up default register map (see table 12) (continued) parallel outputs the parallel bus uses two selectable bus widths, 24 bits and 32 bits. bws selects the bus width according to table 2. in 24-bit mode, din21Cdin28 are not used and are internally pulled down. for both modes, sd, sck, and ws pins are dedicated for i 2 s audio data. the assign - ments of the first 21 or 29 signals are interchangeable and appear in the same order at both sides of the serial link. in image-sensing applications, disabling the i 2 s audio channel (through the internal registers) allows the serialization of three 10-bit camera data streams through din[0:28] plus sd inputs. the parallel bus accepts data clock rates from 8.33mhz to 104mhz for the 24-bit mode and 6.25mhz to 78mhz for the 32-bit mode. serial link signaling and data format the serializers high-speed data serial output uses cml signaling with programmable preemphasis and ac-coupling. the deserializers high-speed receiver uses ac-coupling and programmable channel equaliza - tion. together, the gmsl operates at up to 3.125gbps over stp cable lengths up to 15m. the serializer scrambles and encodes the parallel input bits, and sends the 8b/10b coded signal through the serial link. the deserializer recovers the embedded seri - al clock and then samples, decodes, and descrambles the data onto the parallel output bus. figures 11 and 12 show the serial-data packet format prior to scrambling and 8b/10b coding. for the 24-bit or 32-bit mode, the first 21 or 29 serial bits map to dout[20:0] or dout[28:0], respectively. the audio channel bit (acb) contains an encoded audio signal derived from the three i 2 s inputs (sd, sck, and ws). the forward control channel (fcc) bit carries the forward control data. the last bit (pcb) is the parity bit of the previous 23 or 31 bits. reverse control channel the gmsl uses the reverse control channel to send i 2 c/uart in the opposite direction of the video stream from the deserializer to the serializer. the reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 500 f s after power-up. the serializer temporarily disables the reverse control channel for 350 f s after starting/stop - ping the forward serial link. parallel data-rate selection the deserializer uses the drs input to set the parallel data rate. set drs high to use a low-speed parallel data rate in the range of 6.25mhz to 12.5mhz (32-bit mode) or 8.33mhz to 16.66mhz (24-bit mode). set drs low table 2. bus-width selection using bws register address (hex) power-up default (hex) power-up default settings (msb first) 0x0c 0x00 errthr = 00000000, error threshold set to zero for decoding errors 0x0d 0x00 (read only) decerr = 00000000, zero decoding errors detected 0x0e 0x00 (read only) prbserr = 00000000, zero prbs errors detected 0x12 0x00 mclksrc = 0, mclk is derived from pclkout (see table 4) mclkdiv = 0000000, mclk output is disabled 0x1e 0x02 (read only) id = 00000010, device id is 0x02 0x1f 0x0x (read only) reserved = 0000 revision = xxxx bws input state bus width parallel bus signals used low 24 dout[0:20], ws, sck, sd high 32 dout[0:28], ws, sck, sd
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 17 figure 11. 24-bit mode serial link data format figure 12. 32-bit mode serial link data format table 3. maximum audio sampling rates for various pclk_ frequencies for normal operation with parallel data rates higher than 12.5mhz (32-bit mode) or 16.66mhz (24-bit mode). audio channel the i 2 s audio channel supports audio sampling rates from 8khz to 192khz and audio word lengths from 4 bits to 32 bits. the audio bit clock (sck) does not need to be synchronized with pclkin. the serializer automatically encodes audio data into a single bit stream synchronous with pclkin. the deserializer decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the sd pins on both sides are treated as a regular parallel data pin. pclk_ frequencies can limit the maximum supported audio sampling rate. table 3 lists the maximum audio sampling rate for various pclk_ frequencies. spread- spectrum settings do not affect the i 2 s data rate or ws clock frequency. additional mclk output for audio applications some audio dacs such as the max9850 do not require a synchronous main clock (mclk), while other dacs require mclk to be a specific multiple of ws. if an audio dac chip needs the mclk to be a multiple of ws, syn - chronize the i 2 s audio data with pclk_ of the gmsl, which is typical for most applications. select the pclk_ to be the multiple of ws, or use a clock synthesis chip, such as the max9491, to regenerate the required mclk from pclk_ or sck. for audio applications that cannot directly use the pclkout output, the deserializer provides a divided mclk output on dout28 at the expense of one less par - allel line in 32-bit mode (24-bit mode is not affected). by default, dout28 operates as a parallel data output and 24 bits dout0 dout1 18-bit rgb data hsync, vsync, de audio channel bit forward control- channel bit packet parity check bit note: locations of the rgb data and control signals are interchangeable accordingly on both sides of the link. dout17 dout18 dout19 dout20 ac b fcc pcb 24-bit rgb data hsync, vsync, de additional video data/ control bits audio channel bit forward control- channel bit packet parity check bit note: locations of the rgb data and control signals are interchangeable accordingly on both sides of the link. 32 bits dout0 dout1 dout23 dout24 dout25 dout26 dout27 dout28 ac b fcc pcb word length (bits) pclk_ frequency (drs = low) (mhz) pclk_ frequency (drs = high) (mhz) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 18 _____________________________________________________________________________________ mclk is turned off. set mclkdiv (deserializer register 0x12, d[6:0]) to a non-zero value to enable the mclk output. set mclkdiv to 0x00 to disable mclk and set dout28 as a parallel data output. the output mclk frequency is: src mclk f f mclkdiv = where f src is the mclk source frequency (table 4) and mclkdiv is the divider ratio from 1 to 127. choose mclkdiv values so that f mclk is not greater than 60mhz. mclk frequencies derived from pclk_ (mclksrc = 0) are not affected by spread-spectrum settings in the deserializer. enabling spread spectrum in the serializer, however, introduces spread spectrum into mclk. spread-spectrum settings of either device do not affect mclk frequencies derived from the inter - nal oscillator. the internal oscillator frequency ranges from 100mhz to 150mhz over all process corners and operating conditions. control-channel and register programming the f c uses the control link to send and receive control data over the stp link simultaneously with the high-speed data. configuring the cds pin allows the f c to control the link from either the serializer or the deserializer side to support video-display or image-sensing applications. the control link between the f c and the serializer/ deserializer runs in base mode or bypass mode accord - ing to the mode selection (ms) input of the device con - nected to the f c. base mode is a half-duplex control link and the bypass mode is a full-duplex control link. in base mode, the f c is the host and accesses the registers of both the serializer/deserializer by using the gmsl uart protocol. the f c can also program the peripherals on the remote side by sending the uart packets converted to i 2 c by the device on the remote side of the link (deserial - izer for lcd or serializer for image-sensing applications). the f c communicates with a uart peripheral in base mode (through inttype register settings) using the half-duplex default gmsl uart protocol. the device addresses of the serializer and deserializer in the base mode are programmable. the default values are 0x80 and 0x90, respectively. in base mode, when the peripheral interface uses i 2 c (default), the serializer/deserializer only convert packets that have device addresses different from themselves to i 2 c. the converted i 2 c bit rate is the same as the original uart bit rate. in bypass mode, the f c bypasses the gmsl and communicates with the peripherals directly using its own defined uart protocol. the f c cannot access the gmsl registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one pclk_ period of jitter due to the asynchronous sampling of the uart signal by pclk_. the serializer embeds control signals going to the dese - rializer in the high-speed forward link. do not send a low value longer than 100 f s in either base or bypass mode. the deserializer uses a proprietary differential line coding to send signals back towards the serializer. the speed of the control link ranges from 100kbps to 1mbps in both directions. the serializer/deserializer automati - cally detects the control-channel bit rate in base mode. packet bit rates can vary up to 3.5x from the previous bit rate (see the changing the data frequency section). figure 13 shows the uart protocol for writing and read - ing in base mode between the f c and the serializer/ deserializer. figure 14 shows the uart data format. even parity is used. figures 15 and 16 detail the formats of the sync byte (0x79) and ack byte (0xc3). the f c and the connected slave chip generate the sync byte and ack table 4. f src settings mclksrc setting (register 0x12, d7) data-rate setting bit-width setting mclk source frequency (f src ) 0 high speed 24-bit mode 3 x f pclkout 32-bit mode 4 x f pclkout low speed 24-bit mode 6 x f pclkout 32-bit mode 8 x f pclkout 1 internal oscillator (120mhz typ)
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 19 figure 13. uart protocol for base mode figure 14. uart data format for base mode figure 15. sync byte (0x79) figure 16. ack byte (0xc3) byte, respectively. certain events such as device wake- up and interrupt generate signals on the control path and should be ignored by the f c. all data written to the internal registers do not take affect until after the acknowledge byte is sent. this allows the f c to verify that write commands are processed without error, even if the result of the write command directly affects the serial link. the slave uses the sync byte to synchronize with the host uart data rate automatically. if the int or ms inputs of the device toggle while there is control-channel communication, the control-channel communication can be corrupted. in the event of a missed acknowledge, the f c should assume there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. in base mode, the f c must keep the uart tx/rx lines high for 16 bit times before starting to send a new packet. as shown in figure 17, the remote-side device converts the packets going to or coming from the peripherals from the uart format to the i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 cs data rate is the same as the uart data rate. write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data frmat master writes to slave master writes to slave master reads from slave start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 20 _____________________________________________________________________________________ figure 17. format conversion between uart and i 2 c with register address (i2cmethod = 0) figure 18. format conversion between uart and i 2 c in command-byte-only mode (i2cmethod = 1) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 serializer/deserializer peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 fc serializer/deserializer fc serializer/deserializer serializer/deserializer peripheral : master to slave serializer/deserializer serializer/deserializer serializer/deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) fc serializer/deserializer fc sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheral peripheral s 1 1 1 8 8 8 1 1 1 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n : slave to master s: start p: stop a: acknowledge
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 21 interfacing command-byte-only i 2 c devices the gmsl uart-to-i 2 c conversion interfaces with devices that do not require register addresses, such as the max7324 gpio expander. change the communica - tion method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte-only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. in this mode, the i 2 c master ignores the register address byte and directly reads/writes the subsequent data bytes (figure 18). interrupt control the int of the serializer is the interrupt output and the int of the deserializer is the interrupt input. the interrupt out - put on the serializer follows the transitions at the interrupt input of the deserializer. this interrupt function supports remote-side functions such as touch-screen peripherals, remote power-up, or remote monitoring. interrupts that occur during periods where the reverse control channel is disabled, such as link startup/shutdown, are automati - cally resent once the reverse control channel becomes available again. bit d4 of register 0x06 in the deserializer also stores the interrupt input state. writing to the setint register bit also sets the int output of the serializer. in addition, the f c sets the int output of the serializer by writing to the setint register bit. in normal operation, the state of the interrupt output changes when the interrupt input on the deserializer toggles. line equalizer the deserializer includes an adjustable line equalizer to further compensate cable attenuation at high frequen - cies. the cable equalizer has 11 selectable levels of compensation from 2.1db to 13db (table 5). the eqs input selects the default equalization level at power-up. the state of eqs is latched upon power-up or when resuming from power-down mode. to select other equalization levels, set the corresponding register bits in the deserializer (0x05 d[3:0]). use equalization in the deserializer, together with preemphasis in the serializer to create the most reliable link for a given cable. spread spectrum to reduce the emi generated by the transitions on the serial link and parallel outputs, the deserializer supports spread spectrum. turning on spread spectrum on the deserializer spreads the parallel video outputs. do not enable spread spectrum for both the serializer and dese - rializer. the two selectable spread-spectrum rates at the parallel outputs are q 2% and q 4% (table 6). set the ssen input high to select 2% spread at power-up and ssen input low to select no spread at power-up. the state of ssen is latched upon power-up or when resum - ing from power-down mode. turning on spread spectrum does not affect the audio data stream. changes in the serializer spread settings only affect mclk output if it is derived from pclk_ (mclksrc = 0). table 5. cable equalizer boost levels table 6. parallel output spread boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 power-up default (eqs = high) 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 power-up default (eqs = low) 1010 11.7 1011 13 ss spread (%) 00 no spread spectrum. power-up default when ssen = low. 01 q 2% spread spectrum. power-up default when ssen = high. 10 no spread spectrum. 11 q 4% spread spectrum.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 22 _____________________________________________________________________________________ the device includes a sawtooth divider to control the spread-modulation rate. autodetection or manual pro - gramming of the pclk_ operation range guarantees a spread-spectrum modulation frequency within 20khz to 40khz. additionally, manual configuration of the saw - tooth divider (sdiv, 0x03 d[5:0]) allows the user to set a specific modulation frequency for a specific pclk_ rate. always keep the modulation frequency between 20khz to 40khz to ensure proper operation. manual programming of the spread-spectrum divider the modulation rate relates to the pclk_ frequency as follows: ( ) pclk_ m f f 1 drs mod sdiv = + where: f m = modulation frequency. drs = drs pin input value (0 or 1). f pclk_ = parallel clock frequency (12.5mhz to 104mhz). mod = modulation coefficient given in table 7. sdiv = 5-bit sdiv setting, manually programmed by the f c. to program the sdiv setting, first look up the modulation coefficient according to the part number and desired bit-width and spread-spectrum settings. solve the above equation for sdiv using the desired parallel clock and modulation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 7, set sdiv to the maximum value. sleep mode the deserializer includes a low-power sleep mode to reduce power consumption when it is not attached to the f c lcd applications. set the sleep bit to 1 to initi - ate sleep mode. the deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on waking up the device for different f c and starting conditions. the f c side device cannot enter into sleep mode, and its sleep bit remains at 0. use the pwdn input pin to bring the f c side device into a low-power state. configuration link mode the gmsl includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid parallel clock input. in either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. an internal oscillator provides pclk_ for establishing the serial configuration link between the serializer and deserializer. the parallel output clock and data lines are disabled in the deserializer. the lock output remains low even after a successful configuration link lock. set clinken = 1 on the serializer to turn on the configuration link. the configuration link remains active as long as the video link has not been enabled. the video link overrides the configuration link and attempts to lock when seren = 1. link startup procedure table 8 lists four startup cases for video-display applica - tions. table 9 lists two startup cases for image-sensing applications. in either display or image-sensing applica - tions, the control link is always available after the high- speed data link or the configuration link is established and the gmsl registers or the peripherals are ready for programming. video-display applications for the video-display application, with a remote display unit, connect the f c to the serializer and set cds = low for both the serializer and deserializer. table 8 sum - marizes the four startup cases based on the settings of autos and ms. case 1: autostart mode after power-up or when pwdn transitions from low to high for both the serializer and deserializer, the serial link establishes if a stable pclk_ is present. the serializer locks to pclk_ and sends the serial data to the deserial - izer. the deserializer then detects activity on the serial link and locks to the input serial data. table 7. modulation coefficients and maximum sdiv settings spread-spectrum setting (%) modulation coefficient (decimal) sdiv upper limit (decimal) 4 208 15 2 208 30
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 23 case 2: standby start mode after power-up, or when pwdn transitions from low to high for both the serializer and deserializer, the deserial - izer starts up in sleep mode, and the serializer stays in standby mode (does not send serial data). use the f c and program the serializer to set seren = 1 to establish a video link or clinken = 1 to establish the configura - tion link. after locking to a stable pclk_ (for seren = 1) or the internal oscillator (for clinken = 1), the serializer sends a wake-up signal to the deserializer. the deserial - izer exits sleep mode after locking to the serial data and sets sleep = 0. if after 8ms the deserializer does not lock to the input serial data, the deserializer goes back to sleep, and the internal sleep bit remains uncleared (sleep = 1). case 3: remote side autostart mode after power-up, or when pwdn transitions from low to high, the remote device (deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. the host side (serializer) is in standby mode and does not try to establish a link. use the f c and program the serializer to set seren = 1 (and apply a stable pclk_) to establish a video link, or clinken = 1 to establish the configuration link. in this case, the deserializer ignores the short wake-up signal sent from the serializer. case 4: remote side in sleep mode after power-up or when pwdn transitions from low to high, the remote device (deserializer) starts up in sleep mode. the high-speed link establishes automatically after the serializer powers up with a stable pclk_ and sends a wake-up signal to the deserializer. use this mode in applications where the deserializer powers up before the serializer. image-sensing applications for image-sensing applications, with remote camera unit(s), connect the f c to the deserializer and set cds = high for both the serializer and deserializer. the deserial - izer powers up normally (sleep = 0) and continuously tries to lock to a valid serial input. table 9 summarizes the two startup cases, based on the state of the serializer autos pin. table 8. startup selection for video-display applications (cds = low) case autos (serializer) serializer power-up state ms (deserializer) deserializer power-up state link startup mode 1 low serialization enabled low normal (sleep = 0) both devices power up with the serial link active (autostart). 2 high serialization disabled high sleep mode (sleep = 1) serial link is disabled and the deserializer powers up in sleep mode. set seren = 1 or clinken = 1 in the serializer to start the serial link and wake up the deserializer. 3 high serialization disabled low normal (sleep = 0) both devices power up in nor - mal mode with the serial link disabled. set seren = 1 or clinken = 1 in the serializer to start the serial link. 4 low serialization enabled high sleep mode (sleep = 1) the deserializer starts in sleep mode. link autostarts upon the serializer power-up. use this case when the deserializer pow - ers up before the serializer.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 24 _____________________________________________________________________________________ case 1: autostart mode after power-up, or when pwdn transitions from low to high, the serializer locks to a stable pclkin and sends the high-speed data to the deserializer. the deserializer locks to the serial data and outputs the parallel video data and pclkout. case 2: sleep mode after power-up, or when pwdn transitions from low to high, the serializer starts up in sleep mode. to wake up the serializer, use the f c to send a regular uart frame containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1mbps. the low-power wake-up receiver of the serializer detects the wake-up frame over the reverse control channel and powers up. reset the sleep bit (sleep = 0) of the serializer using a regular control-channel write packet to power up the device fully. send the sleep bit write packet at least 500 f s after the wake-up frame. the serializer goes back to sleep mode if its sleep bit is not cleared within 8ms (typ) after detect - ing a wake-up frame. figure 19. state diagram, cds = low (lcd application) table 9. startup selection for image-sensing applications (cds = high) sleep ms pin setting low high 0 1 sleep bit power-up value config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states int changes from low to high or pwdn = low or send int to serializer pwdn = high, power-on power-down or power-off serial link activity stops or 8ms elapses after fc sets sleep = 1 video link operating prbsen = 0 prbsen = 1 video link prbs test case autos (serializer) serializer power-up state deserializer power-up state link startup mode 1 low serialization enabled normal (sleep = 0) autostart. 2 high sleep mode (sleep = 1) normal (sleep = 0) serializer is in sleep mode. wake up the serializer through the control channel ( f c attached to the deserializer).
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 25 applications information error checking the deserializer checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register (decerr, 0x0d). if a large number of decoding errors are detected within a short duration, the deserializer loses lock and stops the error counter. the deserializer then attempts to relock to the serial data. decerr resets upon successful video link lock, suc - cessful readout of decerr (through uart), or when - ever auto-error reset is enabled. the deserializer does not check for decoding errors during the internal prbs test and decerr is reset to 0x00. err output the deserializer has an open-drain err output. this output asserts low whenever the number of decoding errors exceed the error threshold (errthr, 0x0c) dur - ing normal operation, or when at least one prbs error is detected during prbs test. err reasserts high when - ever decerr (0x0d) resets, due to decerr readout, video link lock, or autoerror reset. autoerror reset the default method to reset errors is to read the respec - tive error registers in the deserializer (0x0d, 0x0e). auto- error reset clears the decoding-error counter (decerr) and the err output ~1 f s after err goes low. autoerror reset is disabled on power-up. enable autoerror reset through autorst (0x06 d6). autoerror reset does not run when the device is in prbs test mode. self prbs test the gmsl link includes a prbs pattern generator and bit-error verification function. set prbsen = 1 (0x04 d5) first in the serializer and then the deserializer to start the prbs test. set prbsen = 0 (0x04 d5) first in the dese - rializer and then the serializer to exit the prbs self test. the deserializer uses an 8-bit register (0x0e) to count the number of detected errors. the control link also controls the start and stop of the error counting. during prbs mode, the device does not count decoding errors and the err output reflects prbs errors only. autoerror reset does not run when the device is in prbs mode. microcontrollers on both sides of the gmsl link (dual c control) usually the f c is either on the serializer side for video- display applications, or on the deserializer side for image-sensing applications. for the former case, both the cds pins are set to low, and for the latter case, the cds pins are set to high. however, if the cds pin of the serializer is low and the cds pin of the deserializer is high, then the serializer/deserializer can both connect to f cs simultaneously. in such a case, the f cs on either side can communicate with the gmsl uart protocol. contentions of the control link may happen if the f cs on both sides are using the link at the same time. the gmsl does not provide the solution for contention avoidance. the serializer/deserealizer do not send an acknowledge frame when communication fails due to contention. users can always implement a higher-layer protocol to figure 20. state diagram, cds = high (camera application) power-on idle serial port locking all states power-down or power-off no signal detected pwdn = high, power on config link operating video link operating video link locked video link unlocked prbsen = 0 prbsen = 1 video link prbs test config link unlocked config link locked signal detected program registers pwdn = low or power-off (reverse channel active)
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 26 _____________________________________________________________________________________ avoid the contention. in addition, if uart communica - tion across the serial link is not required, the f cs can disable the forward and reverse control channel through the fwdccen and revccen bits (0x04 d[1:0]) in the devices. uart communication across the serial link is stopped and contention between f cs no longer occurs. during the dual f c operation, if one of the cds pins on either side changes state, the link resumes the corre - sponding state described in the link startup procedure section. as an example of dual f c use in an image-sensing link, the serializer may be in sleep mode and waiting to be waked up by the deserializer. after wake-up, the serializer-side f c sets the serializer cds pin low and assumes master control of the serializer registers. changing the data frequency both the video data rate (f pclk_ ) and the control data rate (f uart ) can be changed on-the-fly to support appli - cations with multiple clock speeds. slow speed/perfor - mance modes allow significant power savings when a systems full capabilities are not required. enable the gmsl link after pclk_ stabilizes. stop pclkin for 5s and restart the serial link or toggle seren after each change in the parallel clock frequency to recalibrate any automatic settings if a clean frequency change cannot be guaranteed. the reverse control channel remains unavailable for 350 f s after serial link start or stop. limit on-the-fly changes in f uart to factors of less than 3.5 at a time to ensure that the device recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively. lock output loopback connect the lock output to the int input of the device to loopback lock to the serializer. the interrupt output on the serializer follows the transitions at the lock out - put of the deserializer. reverse-channel communication does not require an active forward link to operate and accurately tracks the lock status of the video link. lock asserts for video link only and not for the configu - ration link. gpios the device has two open-drain gpios available. gpio1out and gpio0out (0x06 d3, d1) set the output state of the gpios. the gpio input buffers are always enabled. the input states are stored in gpio1 and gpio0 (0x06 d2, d0). set gpio1out/gpio0out to 1 when using gpio1/gpio0 as an input. staggered parallel data outputs the device staggers the parallel data outputs to reduce emi and noise. staggering outputs also reduce the power-supply transient requirements. by default, the deserializer staggers outputs according to table 10. disable output staggering through the disstag bit (0x06 d7) choosing i 2 c/uart pullup resistors both i 2 c/uart open-drain lines require pullup resistors to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the electrical characteristics table for details). to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the device supports i 2 c/uart rates up to 1mbps. table 10. staggered output delay output output delay relative to dout0 (ns) disstag = 0 disstag = 1 dout0Cdout5, dout21, dout22 0 0 dout6Cdout10, dout23, dout24 0.5 0 dout11Cdout15, dout25, dout26 1 0 dout16Cdout20, dout27, dout28 1.5 0 pclkout 0.75 0
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 27 ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. four capacitorstwo at the serializer output and two at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different volt - age levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml receiver termination resistor (r tr ), the cml driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 i ). this leaves the capacitor selection to change the system time con - stant. use at least 0.2 f f (100v) high-frequency surface- mount ceramic capacitors to pass the lower speed reverse-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the device uses an avdd and dvdd of 3.0v to 3.6v. all single-ended inputs and outputs on the device derive power from an iovdd of 1.7v to 3.6v. the input levels or output levels scale with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. cables and connectors interconnect for cml typically has a differential imped - ance of 100 i . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic- field canceling effects. balanced cables pick up noise as common mode rejected by the cml receiver. table 11 lists the suggested cables and connectors used in the gmsl link. board layout separate the parallel signals and cml high-speed serial signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml, and digital signals. layout pcb traces close to each other and have a 100 i differential characteristic impedance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 i pcb traces do not have 100 i differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. route the pcb traces for a cml channel (there are two conductors per cml channel) in parallel to maintain the differential characteristic impedance. avoid vias. if vias must be used, use only one pair per cml channel and place the via for each line at the same point along the length of the pcb traces. this way, any reflections occur at the same time. do not make vias into test points for ate. keep pcb traces that make up a differential pair equal in length to avoid skew within the differential pair. table 11. suggested connectors and cables for gmsl supplier connector cable jae electronics, inc. mx38-ff a-bw-lxxxxx nissei electric co., ltd. gt11l-2s f-2wme awg28 rosenberger hochfrequenztechnik gmbh d4s10a-40ml5-z dacar 538
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 28 _____________________________________________________________________________________ esd protection the esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. serial inputs meet iso 10605 esd protection and iec 61000-4-2 esd protection. all other pins meet the human body model esd tolerances. the human body model discharge components are c s = 100pf and r d = 1.5k i (figure 21). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 i (figure 22). the iso 10605 discharge components are c s = 330pf and r d = 2k i (figure 23). figure 21. human body model esd test circuit figure 22. iec 61000-4-2 contact discharge esd test circuit figure 23. iso 10605 contact discharge esd test circuit table 12. register table storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1mi r d 1.5ki c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330i storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2ki c s 330pf register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address. 1000000 d0 0 reserved. 0 0x01 d[7:1] desid xxxxxxx deserializer device address. 1001000 d0 0 reserved. 0 0x02 d[7:6] ss 00 no spread spectrum. power-up default when ssen = low . 00, 01 01 q 2% spread spectrum. power-up default when ssen = high . 10 no spread spectrum. 11 q 4% spread spectrum. d5 0 reserved. 0 d4 audioen 0 disable i 2 s channel. 1 1 enable i 2 s channel. d[3:2] prng 00 12.5mhz to 25mhz pixel clock. 11 01 25mhz to 50mhz pixel clock. 10 50mhz to 104mhz pixel clock. 11 automatically detect the pixel clock range. d[1:0] srng 00 0.5 to 1gbps serial-data rate. 11 01 1 to 2gbps serial-data rate. 10 2 to 3.125gbps serial-data rate. 11 automatically detect serial-data rate.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 29 table 12. register table (continued) register address bits name value function default value 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking. 00 01 calibrate spread-modulation rate every 2ms after locking. 10 calibrate spread-modulation rate every 16ms after locking. 11 calibrate spread-modulation rate every 256ms after locking. d5 0 reserved. 0 d[4:0] sdiv 00000 autocalibrate sawtooth divider. 00000 xxxxx manual sdiv setting (see the manual programming of the spread-spectrum divider section). 0x04 d7 locked 0 lock output is low. 0 (read only) 1 lock output is high. d6 outenb 0 enable outputs. 0 1 disable outputs. d5 prbsen 0 disable prbs test. 0 1 enable prbs test. d4 sleep 0 normal mode default value depends on cds and ms pin values at power-up). 0, 1 1 activate sleep mode default value depends on cds and ms pin values at power-up). d[3:2] inttype 00 base mode uses i 2 c peripheral interface. 00 01 base mode uses uart peripheral interface. 10, 11 base mode peripheral interface disabled. d1 revccen 0 disable reverse control channel to serializer (sending). 1 1 enable reverse control channel to serializer (sending). d0 fwdccen 0 disable forward control channel from serializer (receiving). 1 1 enable forward control channel from serializer (receiving).
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 30 _____________________________________________________________________________________ table 12. register table (continued) register address bits name value function default value 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address. 0 1 disable sending of i 2 c register address (command-byte-only mode). d[6:5] hpftune 00 7.5mhz equalizer highpass cutoff frequency. 01 01 3.75mhz cutoff frequency. 10 2.5mhz cutoff frequency. 11 1.87mhz cutoff frequency. d4 pdhf 0 high-frequency boosting enabled. 0 1 high-frequency boosting disabled. d[3:0] eqtune 0000 2.1db equalizer boost gain. 0100, 1001 0001 2.8db equalizer boost gain. 0010 3.4db equalizer boost gain. 0011 4.2db equalizer boost gain. 0100 5.2db equalizer boost gain. power-up default when eqs = high . 0101 6.2db equalizer boost gain. 0110 7db equalizer boost gain. 0111 8.2db equalizer boost gain. 1000 9.4db equalizer boost gain. 1001 10.7db equalizer boost gain. power-up default when eqs = low . 1010 11.7db equalizer boost gain. 1011 13db equalizer boost gain. 11xx do not use. 0x06 d7 disstag 0 enable staggered outputs. 0 1 disable staggered outputs. d6 autorst 0 do not automatically reset error registers and outputs. 0 1 automatically reset error registers and outputs. d5 disint 0 enable interrupt transmission to serializer. 0 1 disable interrupt transmission to serializer. d4 int 0 int input = low (read only). 0 (read only) 1 int input = high (read only). d3 gpio1out 0 output low to gpio1. 1 1 output high to gpio1. d2 gpio1 0 gpio1 is low. 1 (read only) 1 gpio1 is high. d1 gpio0out 0 output low to gpio0. 1 1 output high to gpio0. d0 gpio0 0 gpio0 is low. 1 (read only) 1 gpio0 is high.
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 ______________________________________________________________________________________ 31 table 12. register table (continued) typical application circuit register address bits name value function default value 0x07 d[7:0] 01010100 reserved. 01010100 0x08 d[7:0] 00110000 reserved. 00110000 0x09 d[7:0] 11001000 reserved. 11001000 0x0a d[7:0] 00010010 reserved. 00010010 0x0b d[7:0] 00100000 reserved. 00100000 0x0c d[7:0] errthr xxxxxxxx error threshold for decoding errors. err = low when decerr > errthr. 00000000 0x0d d[7:0] decerr xxxxxxxx decoding error counter. this counter remains zero while the device is in prbs test mode. 00000000 (read only) 0x0e d[7:0] prbserr xxxxxxxx prbs error counter. 00000000 (read only) 0x12 d7 mclksrc 0 mclk derived from pclkout (see table 4). 0 1 mclk derived from internal oscillator. d[6:0] mclkdiv 0000000 mclk disabled. 0000000 xxxxxxx mclk divider. 0x1e d[7:0] id 00000010 device identifier (max9270 = 0x02). 00000010 (read only) 0x1f d[7:4] 0000 reserved. 0000 (read only) d[3:0] revision xxxx device revision. (read only) pclk rgb hsync video ecu uart vsync tx rx int ims audio ws sck sd pclkin din(0:27) din28 cds autos lmn0 lmn1 out- out+ rx/sda tx/scl int ws ms sd sck scl sda pclkout dout(0:27) cds int rx/sda tx/scl lock in+ 1.8v in- ws sd sck dout28/mclk 4.99ki 4.99ki 45.3ki 45.3ki 49.9ki 49.9ki ws sd sck mclk pclk hsync rgb vsync to peripherals display max9850 max9270 lflt lflt gmsl serializer
gigabit multimedia deserializer with spread spectrum and full-duplex control channel max9270 32 _____________________________________________________________________________________ package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos package type package code document no. land pattern no. 56 tqfn-ep t5688+2 21-0135 90-0046
gigabit multimedia deserializer with spread -spectrum and full-duplex control channel max9270 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 33 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/10 initial release 1 1/11 added patent pending to features 1

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